Experiment No.-4 Synthesis and simulation of Half Adder and full Adder.

Experiment No.-4

Aim: Synthesis and simulation of Half Adder and full Adder.

Apparatus Used:-

S.No	Items	Specification	Quantity
1	Computer set	P-4, 2GB DDR	01
2	Software (Tool)	Xilinx 10.1	01

Theory:-
Half Adder:

The half adder is an example of a simple, functional digital circuit built from two logic gates.  The half adder adds to one-bit binary numbers (AB).  The output is the sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to two different gates.  The inputs to the XOR gate are also the inputs to the AND gate.  The input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input to the AND gate receives the same voltage

Full adder:

The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1).   The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers.  The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade.  The carry output from the full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is simply two half adders joined by an OR.

HDL Coding:-

HALF ADDER

library ieee;

use ieee.std_logic_1164.all;

entity andGate is     

   port( A, B : in std_logic;

            S: out std_logic;

            C: out stc_logic);

end andGate;

architecture func of andGate is

begin

   

   S<= A xor B;

   C<= A and B;

end func;

FULL ADDER

I-method:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa is

    Port ( a : in std_logic;

           b : in std_logic;

           c : in std_logic;

           s : out std_logic;

           cr : out std_logic);

end fa;

architecture Behavioral of fa is

begin

         s<= (a xor b) xor c;

         cr<= (a and b) or (b and c) or (c and a);

end Behavioral;

II-method:-

library ieee;

use ieee.std_logic_1164.all;

entity andGate is     

   port( A, B : in std_logic;

            F : out std_logic);

end andGate;

architecture func of andGate is

begin

   F <= A and B;

end func;

library ieee;

use ieee.std_logic_1164.all;

entity xorGate is     

   port(       A, B : in std_logic;

            F : out std_logic);

end xorGate;

architecture func of xorGate is

begin

   F <= A xor B;

end func;

-- At this point we construct the half adder

-- using the AND and XOR gates

library ieee;

use ieee.std_logic_1164.all;

entity halfAdder is

   port( A, B : in std_logic;

    sum, Cout : out std_logic);

end halfAdder;

architecture halfAdder of halfAdder is

   component andGate is -- import AND Gate

      port( A, B : in std_logic;

               F : out std_logic);

   end component;

   component xorGate is -- import XOR Gate

      port( A, B : in std_logic;

               F : out std_logic);

   end component;

begin

   G1 : xorGate port map(A, B, sum);

   G2 : andGate port map(A, B, Cout);

end halfAdder;

--*======================*=================== END HALF ADDER

-- Now we define the OR gate that we need for the Full Adder

library ieee;

use ieee.std_logic_1164.all;

entity orGate is

   port(       A, B : in std_logic;

            F : out std_logic);

end orGate;

architecture func of orGate is

begin

   F <= A or B;

end func;

--*==============================*

--*==============================*

-- We are finally ready to build the Full Adder

library ieee;

use ieee.std_logic_1164.all;

entity fullAdder is

   port( A, B, Cin : in std_logic;

         sum, Cout : out std_logic);

end fullAdder;

--

architecture fullAdder of fullAdder is

   component halfAdder is --import Half Adder entity

      port( A, B  : in std_logic;

        sum, Cout : out std_logic);

   end component;

   component orGate is --import OR Gate entity

      port( A, B : in std_logic;

             F : out std_logic);

   end component;

       

   signal halfTohalf, halfToOr1, halfToOr2: std_logic;

begin

   G1: halfAdder port map(A, B, halfTohalf, halfToOr1);

   G2: halfAdder port map(halfTohalf, Cin, sum, halfToOr2);

   G3: orGate port map(halfToOr1, halfToOr2, Cout);

end fullAdder;

----------------------------------------------------------END

Observation/ Analysis:-

RTL schematic of Half adder

RTL schematic of Full adder